Electro-static discharge (ESD) is always an important factor to be considered in design of integrated circuits. An integrated circuit has an upper limit on a tolerant voltage of the ESD. For example, 10 KV indicates that the integrated circuit may tolerate an ESD voltage in the range of −10 KV to +10 KV. If the ESD voltage exceeds this range, an ESD overrun is present. The ESD overrun may probably result in temporary or permanent damages of components in the integrated circuit.
With respect to a digital circuit, an ESD overrun may probably result in a value hop of a trigger of the basic storage unit in the digital circuit, from “0” to “1” or from “1” to “0”. As a result, circuit calculations related to this trigger encounter errors, and thus the entire circuit is subject to a functionality error. During operation of the circuit, once an ESD overrun is present, operation of the circuit may be subject to errors. If no detection and recovery measures are taken, the circuit may operate in the error state for a long time, which finally causes the integrated circuit to malfunction.
Generally, the ESD detection method is passive, and state of the conventional circuit is detected by using an external main controller. Once it is detected that the circuit state does not comply with expectation, it is considered that an ESD overrun is present, and then the circuit is reset. However, this manner may occupy resources of the external main controller, affect other operations, and have a low efficiency, which fails to detect an ESD overrun in real time.
Therefore, an ESD active detection apparatus is urgently desired to solve the problem in the related art.